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    • 专利摘要:
    command queue for peripheral component. the present invention relates to a peripheral component configured to control an external interface of an integrated circuit. for example, the peripheral component can be a memory interface unit, such as a flash memory interface unit. the internal interface for the peripheral component can be shared between data transfers to / from the external interface and control communications for the peripheral component. the peripheral component can include a command queue configured to store a set of commands to perform a transfer on the interface. a control circuit can be attached to the command queue and can read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. in one embodiment, a macro-memory can store the command sequences to be performed in response to a macro command in the command queue. in one embodiment, a queue of operands can store the data operating for use by the commands.
    公开号:BR112012011096B1
    申请号:R112012011096-9
    申请日:2010-11-08
    公开日:2020-09-24
    发明作者:Douglas C. Lee；Diarmuid P. Ross；Tahoma M. Toelkes
    申请人:Apple Inc.；
    IPC主号:
    专利说明:

    [0001] [0001] The present invention relates to the field of integrated circuits and, more particularly, to the processing of command in a peripheral component in an integrated circuit. Description of the Related Art
    [0002] [0002] In a peripheral interface controller that has significant data bandwidth, one of the challenges that can occur is to provide control input to the peripheral interface controller from an external processor. Typically, the same internal interface for the peripheral controller that transfers data between the peripheral interface controller and the memory is used to provide the control input from the external processor (for example, through a series of recordings to control the records in the controller peripheral interface). While data transfers are taking place, the memory for the peripheral interface can be saturated with data transfers. Consequently, the control inputs for arranging the next set of data transfers can be effectively locked until the current data transfers are complete. During the moment when the control inputs are being supplied, the external peripheral interface controlled by the peripheral interface controller can be inactivated.
    [0003] [0003] A mechanism to reduce contention on the peripheral for the memory interface is to include a processor in the peripheral interface controller, run a program to control the hardware of the peripheral interface controller. However, such a mechanism is expensive in a number of ways: in financial terms to acquire the processor (either as a separate component or an intellectual property that can be incorporated into the design of the peripheral interface controller); in terms of space occupied by the peripheral interface controller when the processor is included; and in terms of power consumed by the processor. In addition, the program to be executed is stored in the system memory and, thus, instruction searches can be completed with data transfers from the peripheral to the memory interface. summary
    [0004] [0004] In one embodiment, an integrated circuit includes a peripheral component configured to control an external interface of the integrated circuit. For example, the peripheral component can be a memory interface unit, such as a flash memory interface unit. The internal interface for the peripheral component can be shared between data transfers to / from the external interface and control communications for the peripheral component. The peripheral component can include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit can be attached to the command queue and can read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands.
    [0005] [0005] In one embodiment, commands in the command queue can be transferred in the command queue at times when data transfers are not taking place on the internal interface. Commands can be available in the command queue to perform the next transfer, for example, when the current transfer is complete. The internal and external interfaces can be used effectively, in some modalities, even on the containment face between data transfers and control transfers on the internal interface. Brief Description of Drawings
    [0006] [0006] The following detailed description refers to the attached drawings, which are briefly described. figure 1 is a block diagram of an integrated circuit, a memory and a flash memory; figure 2 is a block diagram of a flash memory interface embodiment illustrated in figure 1; figure 3 is a flow chart illustrating the operation of a flash memory interface control circuit illustrated in figure 2 in response to the receipt of a recording operation; figure 4 is a table that illustrates a modality of commands supported by the control circuit of the flash memory interface; figure 5 is a flowchart illustrating the operation of a flash memory interface control circuit modality shown in figure 2 in response to reading a command from the first-in-first command buffer (FIFO); figure 6 is a block diagram of an example of using a macro-memory; figure 7 is a flow chart illustrating the operation of a flash memory interface code modality executed by a processor modality shown in figure 1; figure 8 is a block diagram of an embodiment of a system that includes the apparatus illustrated in figure 1; Figure 9 is a block diagram of a modality of a storage medium that can be accessed by computer.
    [0007] [0007] Although the invention is susceptible to various modifications and alternative forms, the specific modalities of it are shown by way of example in the drawings and will be described in detail here. However, it must be understood that the drawings and their detailed description are not intended to limit the invention to the particular form described, but, on the contrary, the intention is to cover all modifications, equivalents and alternatives that fall within the scope of the invention. spirit and scope of the present invention as defined by the embodiments. The titles used here are for organizational purposes only and are not intended to be used to limit the scope of the description. As used throughout this specification, the word "can" is used in a permissive sense (that is, it means that it has the potential to), rather than a mandatory sense (that is, that it means that it should). Similarly, the words "include", "which includes", and "includes" mean including, but not limited to.
    [0008] [0008] Various units, circuits or other components can be described as "configured to" perform a task or tasks. In such contexts, "configured for" is a broad recitation of the structure which, in general, means "having a circuit that" performs the task or tasks during operation. As such, the unit / circuit / component can be configured to perform the task, even when the unit / circuit / component is not currently connected. In general, the circuit that forms the corresponding "configured for" structure may include the hardware and / or memory circuits that store the program instructions that can be executed to implement the operation. The memory may include volatile memory, such as static or dynamic random access memory and / or non-volatile memory, such as optical or magnetic disk storage, flash memory, read-only memories that can be programmed , etc. Similarly, several units / circuits / components can be described to perform a task or tasks, for convenience in the description. These descriptions should be interpreted as including the expression "configured for". Reciting a unit / circuit / component that is configured to perform one or more tasks is expressly intended not to invoke interpretation 35 USC § 112, paragraph six for that unit / circuit / component. Detailed Description of the Modalities
    [0009] [0009] Now, with reference to figure 1, a block diagram of an integrated circuit modality 10 coupled to an external memory 12 and one or more flash memory devices 28A-28B are shown. In the illustrated embodiment, integrated circuit 10 includes a memory controller 14, a system interface unit (SIU) 16, a set of peripheral components, such as components 18A-18B, a flash memory interface unit 30, to access central DMA (CDMA) 20, a processor 22 that includes a level 1 (L1) cache 24, a level 2 (L2) cache 26 and an input / output (I / O) processor (IOP) 32. The memory controller 14 is coupled to a memory interface to which the memory 12 can be attached, and is coupled to the SIU 16. The CDMA controller 20, the L2 cache 26 and the processor 22 (via the L2 cache 26) also are coupled to SIU 16 in the described mode. The L2 cache 26 is attached to processor 22 and CDMA is attached to components 18A-18B, the flash memory interface unit 30 and IOP 32. One or more peripheral components 18A-18B can be attached to external interfaces as well, as peripheral component 18A. In other embodiments, other components can be coupled to the SIU 16 directly (for example, other peripheral components).
    [0010] [00010] The CDMA controller 20 can be configured to perform DMA operations between memory 12, various peripheral components 18A-18B, and / or the flash memory interface unit 30. Various modes can include any number of peripheral components and / or flash memory interface units 30 coupled via the CDMA controller 20. The processor 22 (and, more particularly, the instructions executed by the processor 22) can program the CDMA controller 20 to perform DMA operations. Several modes can program the CDMA 20 controller in several ways. For example, DMA descriptors can be written to memory 12, which describes the DMA operations to be performed and the CDMA controller 20 can include registers that can be programmed to locate DMA descriptors in memory 12. Multiple descriptors can be created for a DMA channel and the described DMA operations can be performed as specified. Alternatively, the CDMA 20 controller can include registers that can be programmed to describe the DMA operations to be performed, and the programming of the CDMA 20 controller can include recording the registers.
    [0011] [00011] In general, a DMA operation can be a transfer of data from a source to a target that is performed by hardware separate from a processor that executes instructions. The hardware can be programmed using instructions executed by the processor, but the transfer itself is performed by the hardware independent of instruction execution on the processor. At least one of a source and target can be a memory. The memory may be system memory (e.g., memory 12), flash memory devices 28A-28B, or it may be an internal memory in integrated circuit 10, in some embodiments. Some DMA operations may have memory as a source and target (for example, a DMA operation between memory 12 and flash memory devices 28A-28B, or a copy operation from one block of memory 12 to another) . Other DMA operations can have a peripheral component as a source or target. The peripheral component can be coupled to an external interface on which the DMA data must be transferred or on which the DMA data must be received. For example, peripheral component 18A can be coupled to an interface on which DMA data must be transferred or on which DMA data must be received. Thus, the DMA operation can include the CDMA controller 20 which reads the data from the source and writes the data to the destination. Data can flow through the CDMA 20 controller as part of the DMA operation. In particular, DMA data for a DMA reading from memory can flow through memory controller 14, through SIU 16, through CDMA controller 20, to peripheral component 18A-18B or to the flash memory interface unit 30 (and possibly the interface to which the peripheral component is attached, if applicable). Data for a DMA write to memory can flow in the opposite direction.
    [0012] [00012] In one embodiment, instructions executed by processor 22 and / or IOP 32 can also communicate with peripheral components 18A-18B and with the flash memory interface unit 30 using read and / or recording calls for scheduled input / output operations (PIO). PIO operations can have an address that is mapped by integrated circuit 10 to a peripheral component 18A-18B or to the flash memory interface unit 30 (and, more particularly, to a register or other source that can be read / written to in the component). The address mapping can be fixed in the address space, or it can be programmed. Alternatively, the PIO operation can be transmitted in a way that is distinguishable from memory read / write operations (for example, using a different command encoding than memory read / write operations in SIU 16, using a sideband signal or control signal to indicate memory vs. IOP, etc.). The PIO transmission may further include the address, which may identify peripheral component 18A-18B or flash memory unit 30 (and the addressed resource) within a PIO address space, for such implementations.
    [0013] [00013] In one embodiment, PIO operations can use the same interconnection as the CDMA 20 controller, and can flow through the CDMA 20 controller, to peripheral components 18A-18B and to the flash memory interface unit 30 Thus, the PIO operation can be granted by processor 22 in SIU 16 (through cache L2 26, in this modality), to the CDMA controller 20, and to the directed peripheral component / flash memory interface unit. Similarly, IOP 32 can grant PIO operations to the CDMA controller 20, which can transmit the PIO operation through the same interconnection to peripheral components 18A-18B or to the flash memory interface unit 30.
    [0014] [00014] Consequently, data transfers for a DMA operation to / from a peripheral component 18A-18B or from the flash memory interface unit 30 may conflict with PIO operations to / from the same peripheral component 18A-18B or the flash memory interface unit 30. For example, the flash memory interface unit 30 can be programmed via PIO operations to perform memory transfers to / from flash memory devices 28A-28B. For write operations, the CDMA 20 controller can DMA the data to be written to the flash memory interface unit 30. For read operations, the CDMA 20 controller can DMA the data to be read from the flash interface unit. flash memory 30. In one embodiment, flash memory devices 28A-28D can be supported on a data transfer page to / from the devices. The page size depends on the device and may not be the same as the page size used as a virtual to physical address translation for memory 12. For example, page sizes of 512 bytes, 2048 bytes and 4096 bytes are generally used. Accordingly, a page can be the unit for transferring data to the memory device in that context.
    [0015] [00015] The flash memory interface unit 30 can be programmed to perform a data transfer page, and the CDMA unit 20 can perform DMA operations for data transfer. If multiple pages are transferred, additional PIO operations can be used to program the flash memory interface unit 30 to perform the next transfer. However, DMA operations can effectively stop additional PIO operations until the current page is complete. Thus, the time that elapses when programming the flash memory interface unit 30 to the next page can result in an idle time on the interface for the flash memory devices.
    [0016] [00016] In one embodiment, the flash memory interface unit 30 can support a queue of commands. The commands for programming the flash memory interface unit 30 for a set of pages to be transferred can be queued in the command queue. Once the DMA operations for the first page begin, the data for programming the flash memory interface unit 30 for subsequent pages can already be stored in the command queue. Consequently, there can be no conflict between the PIO operations to program the flash memory interface unit 30 and the DMA operations for data transfer. Interface utilization for flash memory devices 28A-28B can be increased due to the ability to process command queue commands to configure flash memory controller 30 for the next page to be transferred, while CDMA drive 30 terminates DMA operations for the current page.
    [0017] [00017] In one embodiment, the flash memory interface unit 30 can support a macro memory to store one or more macros. A macro can be a sequence of two or more commands that can be invoked via a macro command. For example, the macro command can be recorded in the command queue, and you can invoke the macro when the macro command is performed by the flash memory interface unit 30. Macros that implement frequently used command sequences can be transferred to the macro memory and thus, fewer commands need to be transferred subsequently. That is, macrocommands can be recorded in the command queue instead of repeatedly recording the commands that are stored in the macro. In one embodiment, the macro command can specify a macro start address and countless words in the macro. Once the number of words has been read from the macro and the corresponding commands have been carried out, the next command in the command queue after the macro command can be carried out. Consequently, return commands can be avoided in the macro, allowing the densest macros in one mode. Other modalities can use the start address and numerous commands as operands. Still other modalities can implement a return command and the macro command can include the start address (but no word / command count) as an operand. In one embodiment, the macro command can also include a loop count operand. The loop count operand can specify numerous iterations of the macro to be performed. Thus, performing the macro command can include reading numerous words starting at the start address and performing them, iterating the number of loop count times, before proceeding to the next command in the command queue after the macro command.
    [0018] [00018] The commands in the command queue and / or commands in the memory can use the operands to control their operation. In some cases, operands can be stored in the command queue. In other cases, operands can be stored in the operand queue. The commands in the command queue or in the memory can specify that the flash memory interface unit 30 loads the operands from the operand queue and operates on the operands. The operand queue can be used with a macro to provide specific occurrence data for the general macro (for example, flash memory addresses, chip enable, etc.). Similarly, the operand queue can provide the operands for the commands in the command queue.
    [0019] [00019] A memory transfer, for use in the present invention, may refer to the transfer of data to / from a memory device (via the interface to the memory device). Thus, a transfer of memory to / from flash memory devices 28A-28B can occur via the interface between flash memory devices 28A-28B and flash memory interface unit 30. Similarly, a transfer of memory to / from memory 12 can occur via the interface between memory 12 and memory controller 14. Memory transfer can occur using a protocol defined by the memory devices. In addition, a command can refer to one or more bytes of data that are interpreted by the hardware in the peripheral component (for example, the flash memory interface unit 30) as specifying a specific operation to be performed by the hardware.
    [0020] [00020] In general, a peripheral component can be a desired circuitry to be included in integrated circuit 10 with the processor. A peripheral component can have defined functionality and the interface by which other components of integrated circuit 10 can communicate with the peripheral component. For example, peripheral components can include video components, such as display controllers, graphics processors, etc .; audio components, such as digital signal processors, mixers, etc .; networking components, such as an Ethernet media access controller (MAC) or a wireless fidelity controller (WiFi); the controllers to communicate with various interfaces, such as the universal serial bus (USB), the peripheral component interconnection (PCI) or its variants, such as the express PCI (PCIe), the serial peripheral interface (SPI), the memory interface flash, etc. The flash memory interface unit 30 can be an example of a peripheral component, and the general properties of a peripheral component described herein can be applied to the flash memory interface unit 30.
    [0021] [00021] Processor 22 can implement any instruction set architecture, and can be configured to execute the instructions defined in that instruction set architecture. Processor 22 can employ any microarchitecture, including scalar, superscalar, channeled, supercanalized, out of order, in order, speculative, non-speculative, etc., or combinations thereof. Processor 22 can include the circuitry and, optionally, can implement microcoding techniques. In the illustrated embodiment, processor 22 may include an L1 cache 24 to store data and instructions for use by processor 22. There may be separate L1 data and instruction caches. The L1 ca-chê (s) can have any capacity and organization (associative set, guided mapping, etc.). In the illustrated mode, an L2 26 cache is also provided. The L2 cache 26 can have any capacity and organization, similar to the L1 cache (s).
    [0022] [00022] Similarly, IOP 32 can implement any instruction set architecture, and can be configured to execute the instructions defined in that instruction set architecture. The instruction set architecture implemented by IOP 32 does not have to be the same as the instruction set architecture implemented by processor 22. In one embodiment, IOP 32 can be a lower power processor and underperforming processor 22. IOP 32 can handle various I / O interface issues (configuring peripheral components to perform the desired operations, dealing with certain errors, etc.). IOP 32 can execute the instructions to record the commands in the command queue in the flash memory interface unit 30, record the macros in the memory in the flash memory interface unit 30, and / or record the operands in the operand queue on the flash memory interface 30. IOP 32 can also execute instructions for serving other peripheral components 18A-18B. Thus, processor 22 can perform other computing tasks or can be turned off to save energy if there are no comparison tasks to be performed. IOP 32 can employ any microarchitecture, including scalar, superscalar, channeled, supercanalized, out of order, in order, speculative, non-speculative, etc., or combinations thereof. IOP 31 can include the circuitry and, optionally, can implement microcoding techniques.
    [0023] [00023] SIU 16 can be an interconnection through which the memory controller 14, processor 22 (through cache L2 26), cache L2 26 and CDMA controller 20 can communicate. SIU 16 can implement any type of interconnection (for example, a bus, a packet interface, point-to-point links, etc.). SIU 16 can be a hierarchy of interconnections, in some modalities.
    [0024] [00024] Memory controller 14 can be configured to receive memory requests from system interface unit 16. Memory controller 14 can be configured to access memory 12 to complete requests (write received data to memory 12 for a write request, or to provide data from memory 12 in response to a read request) using the interface defined for the fixed memory 12. Memory controller 14 can be configured to interface with any type of memory 12, such as dynamic random access memory (DRAM), synchronized DRAM (SDRAM), double data rate SDRAM (DDR, DDR2, DDR3, etc.), DRAM RAMBUS (RDRAM), static RAM (SRAM ), etc. The memory can be arranged as multiple memory banks, such as dual aligned memory modules (DIMMs), single aligned memory modules (SIMMs), etc. In one embodiment, one or more memory chips are attached to the integrated circuit 10 in a pack-in-pack (POP) or chip-on-chip (COC) configuration.
    [0025] [00025] Memory 12 can include one or more memory devices. In general, a memory device can be any component that is designed to store data according to an address provided with the data in a write operation, and to provide that data when the address is used in a read operation. Any of the examples of memory types mentioned above can be implemented in a memory device, and flash memory devices 28A-28B can also be memory devices. A memory device can be a chip, multiple chips connected to a substrate, such as a printed circuit board (for example, SIMM or DIMM, or directly connected to a circuit board to which the IC 10 is attached), etc.
    [0026] [00026] The flash memory interface unit 30 may include the circuitry configured to receive read and write requests for flash memory devices 28A-28B, and configured to interface to flash memory devices 28A-28B for complete read and write requests. In one embodiment, the read and write requests can be sourced from a CDMA 20 controller. The flash memory interface unit 30 can be programmed through one or more control registers (see figure 2 described below) to perform memory transfers to / from flash memory devices 28A-28B (for example, through PIO operations). Flash memory devices 28A-28B can be flash memory, a type of non-volatile memory that is known in the art. In other embodiments, other forms of non-volatile memory can be used. For example, battery-powered SRAM, various types of ROMs that can be programmed, such as ROMs that can be programmed and erased electrically (EEPROMs), etc. can be used. In still other modalities, volatile memory can be used in a similar way to memory 12.
    [0027] [00027] Although the present modality describes the use of the command queue (FIFO), the macro memory, and / or the operand queue (FIFO) in the flash memory interface unit 30, other modalities can implement the characteristics in any peripheral component , with any type of memory or peripheral interface.
    [0028] [00028] It is noted that other modalities may include other combinations of components, including subassemblies or superassemblies of the components shown in figure 1 and / or other components. Although an occurrence of a particular component can be shown in figure 1, other modalities may include one or more occurrences of the particular component.
    [0029] [00029] Now, with reference to figure 2, a block diagram of an embodiment of the flash memory interface unit 30 is shown. In the illustrated embodiment, the flash memory interface unit 30 includes a FIFO command 40, a flash memory interface (IMF) control circuit 42, a macro memory 44, a FIFO operand 46, a flash memory controller (FMC) 48 , a set of FMC control registers 50, data buffers 52A-52B and an error correction / verification unit (ECC) 54. The FIFO 40 command, the FMI control circuit 42, the macro-memory 44, the operating FIFO 46 and buffers 52A-52B are all coupled to an internal interface to the CDMA 20 controller. The FMI 42 control circuit is further coupled to the FIFO 40 command, macro-memory 44, to the FIFO 46 operand and to the control registers FMC 50. The FMC 50 control registers are also coupled to FMC 48, which is coupled to an external interface for flash memory devices. FMC 48 is additionally coupled to buffers 52A-52B. The ECC 54 unit is also coupled to the 52A-52B buffers.
    [0030] [00030] The FMI 42 control circuit can be configured to receive the PIO operations from the CDMA 20 controller. Some PIO operations can be directed to the FIFO 40 command, macro-memory 44 or FIFO 46 operand. For example, the PIO recordings can be used to record the commands in the FIFO 40 command, to transfer the macros in macro-memory 44, or to record the operands in the FIFO 46 operand. Addresses can be assigned to each FIFO 40, macro-memory 44 and the FIFO operand 46, which can be used in the IOP operands to assign the desired resource. For example, FIFOs 40 and 46 can have a single address assigned, since they can operate and a way that first enters, first exits. A PIO recording for the address can cause the FMI 42 control circuit to store the data provided with the recording at the next entry in FIFO 40 or 46. That is, the data can be appended to the end of FIFO 40 or 46, where the commands or operands are removed from the head of FIFO 40 or 46. Macro-memory 44 can have a range of addresses assigned to it, for example, an address per word from macro-memory 44. PIO recordings to addresses can store the word of data provided in the macro word memory address 44.
    [0031] [00031] The FMI 42 control circuit can process the commands in the FIFO 40 command to program multiple FMC 50 control registers to cause the FMC 48 to perform a specific memory transfer to / from the flash memory devices 28A-28B . In one embodiment, the FMC 48 is configured to receive relatively low level control via the FMC 50 control registers, which include the address, chip enable, transfer commands, etc. The commands in the FIFO command 40 can be interpreted by the FMI control circuit 42 and the corresponding FMC control registers 50 can be recorded by the FMI control circuit 42. Similarly, commands to wait for an event can be interpreted through the FMI control circuit 42 to read one or more FMC 50 control registers to detect the event. There may also be direct control signals between the control circuit from FMI 42 to FMC 48, in some modalities (not shown in figure 2) that can be triggered by the control circuit of FMI 42 responsive to commands and / or monitored by FMI 42 control circuit responsive to commands.
    [0032] [00032] The FMI 42 control circuit can be configured to read the commands of the FIFO 40 command in the recorded order. More generally, a command queue may be supported (for example, the FIFO command 40 may not be specifically constructed as a FIFO, such that the entry in the queue may at the same time be visible to the FMI control circuit 42). Similarly, operand FIFO 46 can be a queue of operands, and the control circuit of IMF 42 can read operands from operand FIFO 46 responsive to commands in the command queue or macro-memory 44 in the order that the operands were written.
    [0033] [00033] As mentioned earlier, a macro command can be in the FIFO 40 command, and the IMF control circuit 42 can execute the commands of macro memory 44 in response to the macro command. In other modalities, the macrocommand can be transmitted as a PIO operation to the FMI 42 control circuit. In still other modalities, the macrocommands can be found in the FIFO 40 command or in the PIO operations. The macro command can include a start address in the macro memory and a word count indicating the number of words to be read macro memory 44. The IMF control circuit 42 can carry out the commands in the macro before reading the next command in the command FIFO 40. The words in the macro can include operands in addition to commands, in one mode. Other modalities may use a command count instead of a word count. As mentioned above, the macro command can also include a loop count and the macro can be iterated the number of times indicated by the loop count.
    [0034] [00034] Reading the FIFO 40 command and FIFO 46 operand can include the FMI control circuit 42 that deletes these words from the FIFO. Reading the words of macro-memory 44, on the other hand, may not involve deleting the words, so that macros can be made repeatedly.
    [0035] [00035] The FMC 48 can perform memory transfers in response to the contents of the FMC 50 control registers, recording data read from flash memory devices 28A-28B to buffers 52A-52B or recording data read from buffers 52A-52B for flash memory devices 28A-28B. The 52A-52B buffers can be used in a "ping-pong" manner, in which one of the 52A-52B buffers is being filled with data, while another is being drained. For example, readings from flash memory devices 28A-28B may include FMC 48 that fills one of buffers 52A-52B while another buffer 52A-52B is being drained by the CDMA controller 20 that performs DMA operations into memory 12 Recordings for flash memory devices 28A-28B may include the CDMA 20 controller that fills one of the 52A-52B buffers with data, while FMC 48 drains the other 52A-52B buffer. The ECC unit 54 can generate ECC data for recordings on flash memory devices 28A-28B, and can check ECC data for readings on 28A-28B flash memory devices.
    [0036] [00036] Now, with reference to figure 3, a flow chart is shown that illustrates the operation of an FMI 42 control circuit modality in response to the receipt of a PIO operation from the CDMA 20 controller. Although the blocks are shown in a particular order to facilitate understanding, other orders can be used. The blocks can be made in parallel in combinatorial logic in the IMF 42 control circuit. For example, the decision blocks illustrated in figure 3 can be independent and can be made in parallel. The blocks, the combinations of blocks, and / or the flowchart of a whole can be channeled or can be multiple clock cycles. The FMI control circuit 42 can be configured to implement the operation illustrated in figure 3.
    [0037] [00037] If the PIO recording is directed to the FIFO 40 command (decision block 60, "yes" leg), the FMI 42 control circuit can be configured to update the next entry in the FIFO 40 command with the recording data of PIO (block 62). That is, the PIO recording data can be appended to the end of the FIFO 40 command. If the PIO recording is directed to macro-memory 44 (decision block 64, leg "yes"), the FMI control circuit 42 can be configured to update the targeted input in macro-memory 44 with the PIO recording data (block 66). If the PIO recording is directed to the FIFO 46 operand (decision block 68, "yes" leg), the FMI 42 control circuit can be configured to update the next entry in the FIFO 46 operand with the PIO recording data ( block 70). That is, the PIO recording data can be appended to the end of the FIFO 46 operand. If the PIO recording is directed to a record within the FMC 50 control registers (or other records in the flash memory interface unit 30, in various modalities, decision block 72, leg "yes") the IMF control circuit 42 can be configured to update the address register (block 74).
    [0038] [00038] Next, with reference to figure 4, a table 76 is shown that illustrates an example command set that can be supported in a modality of the flash memory interface unit 30 and, more particularly, of the IMF control circuit. 42. Other modalities can be supported in any other set of commands, including the subsets of the commands shown in figure 4, the subsets of the commands and other commands, and / or a super-set of the commands and other commands. The table includes a "command" column that lists each command, a "operand" column that indicates the operands for a given command, and a "word" column that indicates the number of words in the FIFO 40 command that are occupied by the command .
    [0039] [00039] The format of the commands can vary from modality to modality. For example, in one embodiment, each command can include an operation code byte that identifies the command within the command set (that is, each entry in table 76 can be identified using a different operation code encoding). The remaining bytes in the word or words that make up the command byte can be used to specify the operands for the command. The commands can be stored in the FIFO 40 command or in the macro memory 44, in several modalities.
    [0040] [00040] The address commands (addr0 to addr7 in table 76) can be used to assign the address bytes in the interface to the flash memory devices 28A-28B (in a concentrated manner called the flash memory interface). The digit after "addr" indicates the number of address bytes transmitted, starting with byte 0 of the flash memory interface address. The FMI control circuit 42 can be configured to stop until the address bytes have been transmitted before carrying out the next command, in one mode. The addrX commands can be equivalent to programming the following FMC 50 control registers, in one modality: one or more address registers with the address bytes, and programming a transfer number and the read / write mode in one or more records. Responsive to the read / write mode, the FMC 48 can transmit address bytes on the flash memory interface and can signal an interrupted address in a status register within the FMC 50 control registers. In addition, addrX commands can also include waiting and clearing and the interrupted address in the status record. The addr0 command can be different from the addr1 to addr7 commands in that the address records and the address transfer number record are not programmed. Instead, these records can be programmed using other commands, such as loading next word or loading the FIFO commands described below.
    [0041] [00041] The cmd command can be used to send a flash memory interface command to the flash memory interface. In one embodiment, the flash memory interface commands are one byte. Consequently, the operand of the cmd command can be the command byte can be transmitted on the flash memory interface. The FMI control circuit 42 can be configured to stop until the cmd command is completed on the flash memory interface. The cmd command can be equivalent to programming a command register in the FMC 50 control registers with the command byte; the setting of a command mode bit in another FMC 50 control register; and waiting and clearing an interrupted cmd in a status register within the FMC 50 control registers. Responsive to setting the command mode bit, the FMC 48 can be configured to transmit the command byte on the memory interface flash and can record the interrupted cmd in the status record.
    [0042] [00042] The enable chip command can be used to record a chip enable record from the FMC 50 control registers, which can cause the FMC 48 to trigger the chip enable signals on the flash memory interface based on the operand. and chip enabling.
    [0043] [00043] The page transfer command can be used to initiate a page transfer to / from 28A-28B flash memory devices. In response to the page transfer command, the FMI control circuit 42 can be configured to set an FMC 50 control register bit and wait and clear a broken page in another FMC 50 control register. In response to the FMC 50 control register At the beginning, the FMC 48 can be configured to perform the specified page transfer and the page is interrupted upon completion.
    [0044] [00044] There may be several synchronization commands supported by the FMI 42 control circuit. In general, a synchronization command can be used to specify an event that the FMI 42 control circuit should monitor, and can cause the FMI 42 control circuit wait for the event to occur (that is, wait until the FMI 42 control circuit detects the event) before performing the next command. Thus, synchronization commands can allow sequences of commands to be pre-programmed, and synchronization commands can help ensure the correct timing. For example, multiple page transfers can be pre-programmed and synchronization commands can be used to delay programming the FMC 50 control registers to the next page until the records no longer need the current page (for example, after that the last page data is loaded into the 52A-52B buffer for reading).
    [0045] [00045] In the mode of figure 4, the synchronization command can include wait for rdy, pause, delayed wait, and wait for int. The wait for rdy command can be used to monitor the status of 28A-28B flash memory devices during a page transfer. The wait for rdy command can include wait and clear a specific interruption (for example, page made) in the status record of FMC 50 control records; masking a status byte in the status record with the mask operand, and comparing the masked status byte with the condition of the operand. If the masked status byte matches the condition of the operand, the FMI 42 control circuit can be configured to perform the next command. Otherwise, the FMI control circuit 42 can signal an interruption (for example, for IOP 32 or in processor 22, in various modalities) and can stop the execution of additional commands until IOP 32 / processor 22 of services interrupts .
    [0046] [00046] The pause command can be used to stop the performance of the command by the FMI 42 control circuit. The FMI 42 control circuit can create the performance commands until it does not specifically pause by the software running on IOP 32 / processor 22 that writes a specified enable bit from the FCM 50 control registers.
    [0047] [00047] The FMI 42 control circuit can be configured to pause and resume after countless clock cycles through a time delay command. The number of clock cycles is specified as the time delay command operand. In some embodiments, the delayed standby command can be used to slow down the flash memory interface unit 30, as the performance possible with the use of the FIFO command 40, the memory 44 and the FIFO 46 operand can exceed the rate in the which activities can be performed by the flash memory devices 28A-28B.
    [0048] [00048] The wait for int command can be used to make the FMI 42 control circuit wait for a specific uninterrupted value. The operands can specify the interrupt (IRQ) to be answered, and the state of the irq bit to be answered (for example, set or clear), using the "bit" operand.
    [0049] [00049] The send interrupt command can be used to send a specified interrupt to PIO 32 or processor 22. The send interrupt command operand can specify an interrupt code to write to an FMC 50 control record interrupt code record. , which can cause the interrupt to be sent.
    [0050] [00050] The commands load next word and load from fifo can be used to program several registers in the FMC 50 control. One of the operands of these commands is the register address of the control register to be recorded. In response to the command load next word, the IMF control circuit 42 can read the next word from the FIFO 40 command and write the word to the directed register. In response to the FIFO load command, the FMI control circuit 42 can be configured to read the word from the beginning of the FIFO 46 operand and write the word to the directed register.
    [0051] [00051] The macrocommand can be used to make the IMF control circuit 42 read the commands of macro-memory 44. The macrocommand includes an address operand, a length operand and a loop count operand. The address can identify the first word to be read from macro-memory 44, and the length can identify the length of the macro (for example, in terms of number of commands or number of words). In one embodiment, the number of words length. The loop count can indicate numerous iterations of the macro to be performed. In one embodiment, the loop count operand can be less than the number of iterations (for example, a zero loop count is an iteration, a loop count one is two iterations, etc.). Once the macro is completed, the next FIFO 42 command can be read (that is, there may be no loop in the command in the macro).
    [0052] [00052] The search command can be to search any record in the FMC 50 control registers for a specified value (after masking the value read from the record using the mask field). The FMI control circuit 42 can search the register until the specified value is detected, then proceeds to the next command.
    [0053] [00053] As noted in the description above, the IMF 42 control circuit can monitor several interrupts recorded in one or more status records within the FMC 50 record control as part of carrying out certain commands. The FMI 42 control circuit can clear what was interrupted and complete the corresponding command. In the absence of commands in the FIFO 40 command, interrupts can instead be directed to IOP 32 / processor 22 (if enabled). Consequently, the PIO records operations to the FMC 50 control registers and interrupts to IOP 32 / processor 22 can be another mechanism for performing memory transfers to / from flash memory devices 28A-28B.
    [0054] [00054] Now, with reference to figure 5, a flow chart is shown that illustrates the operation of an FMI control circuit modality 42 to process a command. Although the blocks are shown in a specific order for ease of understanding, other orders can be used. The blocks can be made in parallel in combinatorial logic in the IMF 42 control circuit. The blocks, block combinations and / or the flowchart as a whole can be channeled over multiple clock cycles. The FMI control circuit 42 can be configured to implement the operation illustrated in figure 5.
    [0055] [00055] The FMI control circuit 42 can be configured to read a command from the FIFO 40 command (block 80). If the command is not a macro command (decision block 82, leg "no"), the FMI control circuit 42 can be configured to carry out the command (block 84). Once the command is completed, the FMI 42 control circuit can be configured to check a count of words used to determine if a macro has come to an end. If the command is not part of a macro, the word count can be zero (decision block 86, leg "no"). The FMI control circuit can be configured to check the loop count associated with the remote control. If the command is not part of a macro, the loop count can be zero (decision block 95, leg "no"). The FMI control circuit 42 can be configured to determine if there is another valid command in the FIFO 40 command (decision block 88). That is, the FMI 42 control circuit can be configured to determine whether the FIFO 40 command is empty. If there is another valid command (decision block 88, leg "yes"), the FMI control circuit 42 can be configured to read and process the next command. Otherwise, the FMI control circuit command 42 that processes the circuitry can be inactive until another valid command is recorded in the FIFO 40 command (decision block 88, leg "no").
    [0056] [00056] If the command is a macro command (decision block 82, leg "yes"), the IMF control circuit 42 can be configured to start word count for the macro command length operand and to start counting loop for the macro command loop count operand (block 90). The FMI control circuit 42 can also read a command from macro memory 44 (block 92). Specifically, in this case, the IMF control circuit 42 can read the first word of the address in macro memory 44 provided as the address of the operand in the macro command. The FMI control circuit 42 can be configured to perform the command (block 84), and can be configured to check the word count. The word count can be greater than zero (decision block 86, "yes" leg), and the IMF control circuit 42 can be configured to reduce the word count and to read the next command from macro-memory 44 (for example , by adding the address) (blocks 94 and 96). The FMI control circuit 42 can be configured to process the next command (return to decision block 82 in the flowchart of figure 5). If the word count is zero (decision block 86, leg "no"), the FMI control circuit 42 can be configured to check the loop count. If the loop count is greater than zero (decision block 95, "yes" leg), another iteration of the macro must be performed. The FMI control circuit 42 can reduce the loop count (block 97), reset the word count and macro address (block 99), and read the next command from memory 44 (ie the first command of the macro) (block 96). If both the word count and the loop count are zero (decision block 86 and 88, leg "no"), the macro is completed and the FMI control circuit 42 can check the next valid command in the command queue 40 (decision block 88).
    [0057] [00057] It is observed that since each command is verified as a macro command, the macro commands can also be stored in macro-memory 44. Consequently, the macros can be "grouped", although the last macro to be performed returns to the command FIFO 40 so that there is no real grouping in the sense that the macros do not return to the macros that called them.
    [0058] [00058] Now, with reference to figure 6, a block diagram of an example of using macros to perform a multi-page recording to a 28A or 28B flash memory device is shown. Macromemory 44 content is shown, which includes three command sections. Between macro address 0 and N-1, N macro words 100 to end a recording for the previous page are stored. Between macro address N and N + M-1, M macro words 102 to start recording to a next page are stored. Between the address of the macro + N + M and N + M + P-1, P words of 104 are stored to finalize the last page of a recording into memory.
    [0059] [00059] A set of commands in the FIFO 40 command is illustrated in figure 6, with a FIFO head at the top of the FIFO 42 command and subsequent commands in the FIFO that proceed neither downwards in the FIFO 40 command as shown in figure 6. The first command is macro N, M. The command calls macro 104, which begins with the word N, and executes M words (that is, macro 102 as shown in figure 6). Thus, recording for the first page starts. Subsequent page recordings can be performed using macro 0, N + M commands. These commands cause macro 100 and macro 102 to be performed. Recording to the previous page can be completed (macro 100) and recording to the next page can be started (macro 102). The last page can be saved using the macro command 0, N + M + P. This command causes macros 100, 102, and 104 to be executed, completing the recording for the second to the last page (macro 100), making the recording on the last page (macro 102) and completing the recording on the last page and closing a 28A or 28B flash memory device (macro 104). In this example, the loop count operand for each macro command is zero (an iteration). However, in another example, shown below the first example in figure 6, the loop count operand can be used to make the commands in the command queue even more efficient. The loop count of the macro command N, M for the first page and the macro command 0, N + M + P for the last page can still be zero, specifying an iteration. However, the middle pages of the recording can all be made using a macro command (macro 0, N + M) with a loop count operand equal to the page count (C) minus 3. The count of loop is C-3 to account for the first and last page, as well as the fact that the operating counting circuit is less than the desired number of iterations in this mode. As macros 100, 102, and 104 illustrate, by carefully placing macros in macro-memory 44, dense and effective macros can result. Macros can use the FIFO load commands to use different operands for each page write operand, and the operands for each page can be loaded in the FIFO 46 operand before starting the commands in the FIFO 40 command.
    [0060] [00060] The commands included in macro 102 can establish the address to be recorded, the chip enable, etc. The commands included in macro 100 can include page transfer to transfer the previous page to memory, and commands to check for errors and synchronize the next page transfer (which can be initiated through macro 102). Macro 104 can include the final page transfer command, as well as commands to check for errors and to close the flash memory device that was the destination of the recordings, to disable the active page / region and / or perform any other operations, as specified for the flash memory device.
    [0061] [00061] Now, with reference to figure 7, a flow chart illustrating the operation of a flash code to be executed by IOP 32 and / or by processor 22 is shown. Although the blocks are shown in a specific order for ease of understanding, other orders can be used. The flash code can include instructions that, when executed by IOP 32 and / or processor 22, can implement the operation illustrated in figure 7.
    [0062] [00062] The flash code can be executed at any time during the operation of the integrated circuit 10. For example, the flash code can be executed to start the flash memory interface unit 30. The flash code can also be executed at any time that flash memory 30 is inactive, but can be accessed, to reconfigure macros in macro memory 44, etc.
    [0063] [00063] The flash code can transfer any desired macros to macro-memory 44 (block 110). If the macros already stored in memory 44 are the desired macros, or if there are no desired macros, block 110 can be ignored. The flash code can also transfer any operands to be used by commands or macros (block 112), and block 112 can be ignored if there are no operands to be transferred. The flash code can transfer the commands to be performed (block 114), and the performance of the command can start on the flash memory interface unit 30. If the additional commands are already transferred (decision block 116, leg "yes"), the flash code can transfer additional commands (block 114). If new operands or macros are transferred (decision block 118, leg "yes"), the flash code can return to blocks 110 and / or 112 to transfer them. System and Storage Medium that can be accessed by Computer
    [0064] [00064] Next, with reference to figure 8, a block diagram of a modality of a system 150 is shown. In the illustrated embodiment, the system 150 includes at least one occurrence of an integrated circuit 10 (of figure 1) coupled to one or more peripherals 154 and an external memory 158. External memory 158 can include memory 12. A power supply 156 is also provided, which supplies the supply voltages for the integrated circuit 10, as well as one or more supply voltages for memory 158 and / or peripherals 154. In some embodiments, more than one occurrence of integrated circuit 10 may be present included (and more than one external memory 158 can also be included).
    [0065] [00065] Peripherals 154 can include any desired circuit set, depending on the type of system 150. For example, in one embodiment, system 150 can be a mobile device (for example, a personal digital assistant (PDA), smartphone, etc.) and peripherals 154 may include devices for various types of wireless communication, such as wifi, Bluetooth, cell phone, global positioning system, etc. Peripherals 154 may also include additional storage, which includes RAM storage, solid state storage, or disk storage. Peripherals 154 may include user interface devices, such as a display screen, which includes display screens or multitouch display screens, a keyboard or other input devices, microphones, speakers, etc. In other embodiments, system 150 can be any type of computing system (for example, desktop personal computer, laptop, workstation, netbook, etc.).
    [0066] [00066] External memory 158 can include any type of memory. For example, external memory 158 can be SRAM, dynamic RAM (DRAM), such as synchronized DRAM (SDRAM), SDRAM, DRAM RAMBUS dual data rate (DDR, DDR2, DDR3, etc.), etc. External memory 158 may include one or more memory modules to which the memory devices are mounted, such as the only aligned memory modules (SIMMs), the aligned dual memory modules (DIMMs), etc.
    [0067] [00067] Now, with reference to figure 9, a block diagram of a computer-accessible storage medium 200 is shown. In general, a storage medium that can be accessed by a computer can include any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, a storage medium that can be accessed by computer may include a storage medium, such as magnetic or optical media, for example, disk (fixed or removable), tape, CD-ROM, DVD-ROM, CD-R , CD-RW, DVD-R, DVD-RW, or Blu-Ray. The storage medium may also include volatile or non-volatile memory media, such as RAM (for example, synchronized dynamic RAM (SDRAM), DRAM Rambus (RDRAM), static RAM (SRAM), etc.), ROM , flash memory, non-volatile memory (for example, flash memory) accessible through a peripheral interface, such as the universal serial bus (USB) interface, a flash memory interface (IMF), a serial peripheral interface (SPI), etc. The storage medium can include microelectromechanical systems (MEMS), as well as the storage medium that can be accessed through a communication medium, such as a network and / or a wireless link. The storage medium that can be accessed by computer 200 in figure 5 can store flash code 202, which can include code by IOP 32 and / or processor 22. Flash code 202 can include instructions that, when executed, implement the operation described above with respect to figure 7. In general, the computer-accessible storage medium 200 can store any set of instructions that, when executed, implement some or all of the operation shown in figure 7. Additionally, the computer-accessible storage medium 200 may store one or more macros 204 to be transferred to macro-memory 44, one or more operands to be transferred to FIFO operand 36, and / or one or more commands to be transferred to the FIFO command 40. A carrier medium can include the storage medium that can be accessed by computer, as well as the transmission medium, such as wired or wireless transmission.
    [0068] [00068] Numerous variations and modifications will become evident to those skilled in the art, once the above presentation is fully observed. The embodiments are intended to be interpreted to cover all such variations and modifications.
    权利要求:
    Claims (18)
    [0001]
    Apparatus for controlling an external interface in an integrated circuit (10), the apparatus comprising: a controller (48) configured to communicate on the external interface; a command queue (40) configured to store a plurality of commands that cause a transfer on the external interface, wherein the plurality of commands in the command queue (40) is removed from the command queue (40) in response to the execution of the plurality of commands; and a control circuit (42) coupled to the command queue (40) and the controller (48), where the control circuit (42) is configured to read the plurality of commands from the command queue (40) and is configured to start the corresponding operations on the controller (48) to carry out the transfer; characterized by the fact that it still comprises a macro-memory (44) configured to store a second plurality of commands, and in which the second plurality of commands remains in the macro-memory (44) even when the second plurality of commands has been executed, and in which at least at least one of the plurality of commands in the command queue (40) is a macro command that causes commands in the macro-memory (44) to be executed, and in which the macro command specifies an address of a first command in the macro-memory (44) that must be executed and a number of words to be read starting with the first command, and in which the control circuit (42) is configured to read the number of words from the macro memory (44) in response to the macro command and, subsequently, execute the next command in the command queue (40) after the macro command without requiring a return command in the macro memory (44), whereby the second plurality of commands excludes return commands to return air to the command line (40).
    [0002]
    Apparatus according to claim 1, characterized by the fact that it additionally comprises a plurality of control registers (50) coupled to the controller (48) and the control circuit (42), in which the controller (48) is configured to communicate on the external interface responsive to a content of a plurality of control registers (50), and where the plurality of commands includes one or more commands that cause the control circuit (42) to update one or more of the plurality of control records (50).
    [0003]
    Apparatus according to claim 2, characterized by the fact that the control circuit (42) is configured to receive an operation on an internal interface within the integrated circuit (10), in which the operation indicates a direct update of one of a plurality of control registers (50), and wherein the control circuit (42) is configured to update one of the control registers (50) in response to receiving the operation.
    [0004]
    Apparatus according to claim 3, characterized by the fact that the control circuit (42) is further configured to receive the plurality of commands on the internal interface, and in which the control circuit (42) is configured to record the plurality of commands in the command queue (40) responsive to the reception of a plurality of commands.
    [0005]
    Apparatus according to claim 1, characterized by the fact that the external interface is a memory interface, and in which the plurality of commands includes a first command that causes the controller (48) to direct an address to one or more memory devices (28A, 28B) that are coupled to the memory interface.
    [0006]
    Apparatus according to claim 5, characterized by the fact that the plurality of commands includes a second command that causes the controller (48) to direct one or more specified chip enabled signals to one or more memory devices (28A, 28B).
    [0007]
    Apparatus according to claim 5, characterized in that the plurality of commands includes a second command that causes the controller (48) to transfer a data page between the integrated circuit (10) and one or more memory devices (28A, 28B).
    [0008]
    Apparatus according to claim 5, characterized by the fact that the memory interface is a flash memory interface.
    [0009]
    Apparatus, according to claim 1, characterized by the fact that the macro command still specifies a loop count operand that indicates numerous iterations of the second plurality of commands that must be performed.
    [0010]
    Apparatus according to claim 9, characterized by the fact that the second plurality of commands includes a second macro command that specifies a second address of a second command in the macro memory (44) and a second number of words to be read, and in which the control circuit (42) is configured to return to the subsequent command queue (40) to carry out the commands in the second number of words beginning with the second command.
    [0011]
    Apparatus according to claim 10, characterized by the fact that the apparatus includes a queue of operands (46) configured to store the operand data accessible by the commands in the command queue (40) and in the macro-memory (44).
    [0012]
    Method, which comprises the steps of: reading a plurality of commands from a command queue (40) into a memory interface unit (30) of an integrated circuit (10), wherein the plurality of commands in the command queue (40) is removed from the command queue (40) in response to carrying out the plurality of commands; and cause a controller (48) to communicate on an external interface of the integrated circuit (10) to one or more memory devices (28A, 28B) coupled to the external interface responsive to the plurality of commands in the command queue (40), in that the plurality of commands causes a memory transfer between one or more memory devices (28A, 28B) and the integrated circuit (10), wherein a memory transfer comprises one or more pages of data; characterized by the fact that the memory interface unit (30) further includes a macro-memory (44) for storing a second plurality of commands, and wherein the second plurality of commands remains in the macro-memory (44) even when the second plurality of commands has been executed, in that at least one of the plurality of commands in the command queue (40) is a macro command that causes commands in the macro-memory (44) to be executed, and in which the macro command specifies an address of a first command in the macro-memory (44) that must be executed and a number of words to be read starting with the first command; and read the number of words from the macro-memory (44) in response to the macro-command and subsequently carry out the next command in the command queue (40) after the macro-command without requiring a return command in the macro-memory (44), through which a plurality of commands exclude return commands to return to the command queue (40).
    [0013]
    Method according to claim 12, characterized in that the plurality of commands includes a first command that causes the controller (48) to transmit an address to one or more memory devices (28A, 28B), a second command which causes the controller (48) to transmit a chip enable set to one or more memory devices (28A, 28B), and at least a third command which causes the controller (48) to transfer a page of data.
    [0014]
    Method according to claim 12, characterized by the fact that the plurality of commands comprises a first command that causes the controller (48) to transmit a command corresponding to one or more memory devices (28A, 28B) at the interface, the corresponding command defined in a memory interface protocol for one or more memory devices (28A, 28B).
    [0015]
    Method according to claim 14, characterized in that one or more memory devices (28A, 28B) comprise one or more flash memory devices (28A, 28B), and the corresponding command comprises a command byte defined on a flash memory interface supported by one or more flash memory devices (28A, 28B).
    [0016]
    Method, according to claim 12, characterized by the fact that the macro command still specifies a loop count operand that indicates numerous iterations of the second plurality of commands that must be performed.
    [0017]
    Method according to claim 16, characterized by the fact that the second plurality of commands includes a second macro command that specifies a second address of a second command in the macro-memory (44) and a second number of words to be read, and in which the method additionally includes re-going to the subsequent command queue (40) to carry out the commands on the second number of words beginning with the second command.
    [0018]
    Method, according to claim 17, characterized by the fact that it still comprises operand data accessible from a queue of operands (46) for commands in the command queue (40) and in the macro-memory (44).
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    法律状态:
    2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according art. 34 industrial property law|
    2019-07-30| B06U| Preliminary requirement: requests with searches performed by other patent offices: suspension of the patent application procedure|
    2020-05-05| B09A| Decision: intention to grant|
    2020-09-24| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 08/11/2010, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US12/615,587|US8131889B2|2009-11-10|2009-11-10|Command queue for peripheral component|
    US12/615,587|2009-11-10|
    PCT/US2010/055769|WO2011059897A1|2009-11-10|2010-11-08|Command queue for peripheral component|
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